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IDT74FCT16373AT/CT FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 16-BIT TRANSPARENT LATCH
IDT74FCT16373AT/CT
FEATURES:
* * * * * * * *
0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1A (max.) VCC = 5V 10% High drive outputs (-32mA IOH, 64mA IOL) Power off disable outputs permit "live insertion" Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25C * Available in SSOP and TSSOP packages
DESCRIPTION:
The FCT16373T 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. These high-speed, low-power latches are ideal for temporary storage of data. They can be used for implementing memory address latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls are organized to operate each device as two 8-bit latches, or one 16-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT16373T is ideally suited for driving high-capacitance loads and lowimpedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.
FUNCTIONAL BLOCK DIAGRAM
1OE
2OE
1LE
2LE
1D 1
D
1O 1
2D 1
D
2O 1
C
C
TO SEVEN OTHE R CHANNELS
TO SEVEN OTHE R CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 2002 Integrated Device Technology, Inc.
NOVEMBER 2002
DSC-5454/2
IDT74FCT16373AT/CT FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1OE 1O1 1O2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to 7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1LE 1D1 1D2
VTERM(2) TSTG IOUT
VTERM(3) Terminal Voltage with Respect to GND
GND
1O3 1O4
GND
1D3 1D4
VCC
1O5 1O6
VCC
1D5 1D6
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Outputs and I/O terminals for FCT162XXX.
GND
1O7 1O8 2O1 2O2
GND
1D7 1D8 2D1 2D2
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. 6 8 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
GND
2O3 2O4
GND
2D3 2D4
PIN DESCRIPTION
Pin Names xDx xLE xOE xOx Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) 3-State Outputs Description
VCC
2O5 2O6
VCC
2D5 2D6
GND
2O7 2O8 2OE
GND
2D7 2D8 2LE
FUNCTION TABLE(1)
Inputs xDx H L X
NOTE: 1. H = HIGH voltage level L = LOW voltage level X = Don't care Z = High-impedance
SSOP/ TSSOP TOP VIEW
Outputs xOE L L H xOx H L Z
xLE H H X
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IDT74FCT16373AT/CT FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 10%
Symbol VIH VIL IIH IIL IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins)(5) Input HIGH Current (I/O pins)(5) Input LOW Current (Input pins)(5) Input LOW Current (I/O pins)(5) High Impedance Output Current (3-State Output pins)(5) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Max VIN = GND or VCC VCC = Min., IIN = -18mA VCC = Max., VO = GND(3) -- VCC = Max. VO = 2.7V VO = 0.5V VI = GND Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC Min. 2 -- -- -- -- -- -- -- -- -80 -- -- Typ.(2) -- -- -- -- -- -- -- -- -0.7 -140 100 5 Max. -- 0.8 1 1 1 1 1 1 -1.2 -250 -- 500 V mA mV A A Unit V V A
OUTPUT DRIVE CHARACTERISTICS
Symbol IO VOH Parameter Output Drive Current Output HIGH Voltage VCC = Max., VO = VCC = Min. VIN = VIH or VIL VOL IOFF Output LOW Voltage Input/Output Power Off Leakage(5) VCC = Min. VIN = VIH or VIL VCC = 0V, VIN = or VO 4.5V -- -- 1 A
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. This test limit for this parameter is 5A at TA = -55C.
Test Conditions(1) 2.5V(3) IOH = -3mA IOH = -15mA IOH = -32mA(4) IOL = 64mA
Min. -50 2.5 2.4 2 --
Typ.(2) -- 3.5 3.5 3 0.2
Max. 180 -- -- -- 0.55
Unit mA V V V V
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IDT74FCT16373AT/CT FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open xOE = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle xOE = GND xLE = VCC One Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle xOE = GND xLE = VCC Sixteen Bits Toggling VIN = VCC VIN = GND Min. -- -- Typ.(2) 0.5 60 Max. 1.5 100 Unit mA A/ MHz
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
0.6
1.5
mA
--
0.9
2.3
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
2.4
4.5(5) 16.5(5)
--
6.4
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
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IDT74FCT16373AT/CT FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW tSK(o) Parameter Propagation Delay xDx to xOx Propagation Delay xLE to xOx Output Enable Time Output Disable Time Set-up Time HIGH or LOW, xDx to xLE Hold Time HIGH or LOW, xDx to xLE xLE Pulse Width HIGH Output Skew(3) Condition(2) CL = 50pF RL = 500 FCT16373AT Min.(2) Max. 1.5 5.2 2 1.5 1.5 2 1.5 5 -- 8.5 6.5 5.5 -- -- -- 0.5 FCT16373CT Min.(2) Max. 1.5 3.6 2 1.5 1.5 2 1.5 5 -- 3.7 4.4 3.9 -- -- -- 0.5 Unit ns ns ns ns ns ns ns ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
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IDT74FCT16373AT/CT FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 7.0V 500 V IN Pulse Generator D.U.T. 50pF RT 500 CL V OUT
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
DATA INPUT tSU TIM ING INPUT ASYNCHRONOUS CONTROL PRES ET CLEA R ETC. SYNCHRONOUS CONTROL PRES ET CLEA R CLOCK ENABLE ETC. tREM
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE
1.5V
1.5V
tSU
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE SAM E PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE P HASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V DISABLE 3V CONTROL INPUT tPZL OUTPUT NORM ALLY LOW SW ITCH CLOSED tPZH OUTPUT NORM ALLY HIGH SW ITCH OPEN 3.5V 1.5V 0.3V tPHZ 0.3V 1.5V 0V 0V VOH tPLZ 1.5V 0V 3.5V VOL
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDT74FCT16373AT/CT FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX FCT Temp. Range XXX Family XXXX Device Type XX Package X Process Blank Industrial
PV PA
Shrink Small Outline Package Thin Shrink Small Outline Package
373AT 373CT
16-Bit Transparent Latch
16
Double-Density, 5 Volt, High Drive
74
- 40C to +85C
DATA SHEET DOCUMENT HISTORY 5/22/2002 Removed TVSOP package 11/21/2002 Removed Military temp grade and Standard speed
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